1. Field of the Invention
The present invention relates to a mounting for a package containing a semiconductor chip.
2. Description of the Related Art
A typical package for a semiconductor chip includes an internal leadframe, which functions as a substrate for the package. The leadframe includes a central metal die pad and a plurality of leads. A body of a hardened, insulative encapsulant material covers the die, die pad, and an inner portion of each of the leads. The encapsulant material is provided both above and below the die pad and leads.
The semiconductor chip is mounted on the die pad and is electrically connected to the leads. In particular, the chip includes a plurality of bond pads, each of which is electrically connected by a conductor (e.g., a bond wire) to an encapsulated inner portion of one of the leads. An outer portion of each lead extends outward from the body of encapsulant material, and serves as an input/output terminal for the package. The outer portion of the leads may be bent into various configurations, such as a J lead configuration or a gull wing configuration.
Customers of such packages typically mount the package on an larger substrate, such as motherboard. The outer lead portions are soldered to metal traces of a mounting surface of the motherboard. The outer lead portions space the body of encapsulant material (and accordingly the chip, die pad, bond wires, and inner leads) a vertical distance above the mounting surface. Accordingly, the package has a relatively large height above the mounting surface, which is undesirable in some applications.
Lately, practitioners have attempted to make packages thinner by providing the die pad and leads at a bottom surface of the body of encapsulant material, rather than in the middle of the body of encapsulant material. Such packages enjoy a lower height than the standard leadframe packages mentioned above, since there is no encapsulant beneath the die pad and leads. Nonetheless, the height of the package above the mounting surface may still be too great for some applications, since the encapsulant must still extend over the die. Accordingly, a solution is necessary for applications where the height of the package above the mounting surface of the motherboard must be as small as possible.
A mounting for a package containing a semiconductor chip is disclosed, along with methods of making such a mounting. The mounting includes a substrate having a mounting surface with conductive traces thereon, and an aperture extending through the substrate. The package includes a base, such as a leadframe or a metallized laminate sheet, with input/output terminals for electrically connecting the package to the traces of the mounting surface. At least one chip is provided on a first side of the base of the package. The chip is electrically connected through the package (i.e., directly or indirectly) to the input/output terminals of the package. A cap, which may be a molded encapsulant material, is provided on the first side of the base over the chip. The package is mounted on the substrate so that the cap extends into the aperture of the substrate. A circumferential portion of the first side of the base outside of the cap is juxtaposed with the mounting surface so as to support the package and allow the input/output terminals of the package to be electrically connected to juxtaposed traces of the mounting surface of the substrate. Because the cap is within the aperture, a height of the package over the mounting surface is much less than in a conventional mounting, yielding distinct advantages in applications where the height of the package over the mounting surface is critical.
Various exemplary embodiments of mountings and packages for the mountings also are disclosed herein. For example, a mounting for a stack of packages is disclosed, wherein a second package is mounted on a first package that is mounted on the substrate. Alternatively, two packages may be mounted on opposite sides of the substrate, with the cap of each package in the aperture and facing the cap of the other package. In addition, embodiments for electrically connecting the package to the traces of the substrate using clips on the substrate, or channels in the substrate, are disclosed. Such embodiments can allow for a snap-in, solderless electrical connection of the package to the substrate.